The present invention relates to liquid crystal displays (LCD) and, more particularly, to a novel liquid crystal display comprising a plurality of cells, or pixels (picture elements), with each cell having a redundant field-effect transistor (FET) and a redundant crossover structure for the pixel address lines, both connected by laser-fusible links to the display.
A liquid crystal display device typically comprises a pair of flat panels (usually a glass substrate and a cover glass) sealably containing a quantity of liquid crystal material, such as a dichroic dye guest/host system or a twisted nematic formulation. One of the flat panels will usually have conductive material disposed on, and substantially completely covering, an inner surface to form a "ground plane" electrode. A plurality of electrodes, formed from a transparent conductive material such as indium tin oxide (ITO), will be disposed on the opposite panel and will usually be arranged in uniform columns and rows to form an X-Y matrix structure. These electrodes are generally referred to as "pixel" electrodes. Thus, in a liquid crystal display a typical cell or pixel includes liquid crystal material disposed between a pixel electrode and a ground electrode, which effectively forms a capacitor disposed between the two flat panels. If the liquid crystal display is to operate by reflected light, as in a digital watch or calculator display, only the opposite panel (on which the ITO electrodes are disposed) need be transparent; the other panel will be formed with a reflective surface. If the liquid crystal display is to be light transmissive, then both flat panels should be transparent and the ground plane electrode should also be formed from a transparent material (such as ITO and the like).
A semiconductor switch, such as a thin-film field-effect transistor (FET) and the like, is integrally formed with each pixel to control operation of that pixel in the display. FETs are preferred in LCDs because of their potentially small size, low power consumption, favorable switching speeds, ease of fabrication, and compatibility with conventional LCD structures.
Electrical communication with the individual pixel FETs is accomplished by a plurality of X-address lines or scan lines, typically one for each row (or column) of pixels, and a plurality of Y-address lines or data lines, one for each column (or row) of pixels. The scan lines are usually connected to the gate electrodes of the pixel FETs and the data lines are usually connected to the source electrodes. The drain electrode of each FET is connected to the pixel electrode. An individual pixel may be addressed by applying a voltage of sufficient magnitude to one of the scan lines to cause the FETs in the row corresponding to the scan line to "switch-on" to a conducting state. If a data voltage is applied to a data line while an FET in the column corresponding to the data line is in an "on" state, the pixel capacitor will charge and store the data voltage after the scan line voltage has decreased to a level sufficient to turn-off the FET. Each pixel in the display may be individually addressed in this manner. Depending upon the magnitude of the data voltage applied to the pixel electrode, the optical properties of the liquid crystal material are altered. The data voltage magnitude may be such as to: allow no light transmission through the pixel (off); allow maximum light transmission through the pixel (on); or provide an intermediate gray scale level of light transmission.
Short-circuits between the data lines and scan lines (at locations where these address lines cross over one another), short-circuits within the FETs, and short-circuits between the FETs and the scan or data lines, are the major sources of defects adversely affecting operation of amorphous silicon liquid crystal displays. Shorts may also exist between the ITO of the pixel electrodes and the data and scan address lines where the ITO hasn't been completely etched away to provide a spacing between the pixel and the adjacent address lines.
The scan and data address lines are insulated from each other at their crossover locations by a thin layer of an insulation material, such as silicon nitride (SiN). The data and scan lines can short to one another at the crossover locations through holes which may inadvertently develop in the insulation layer during device fabrication. Typically, the metallization for the data and scan lines is deposited by sputtering during different process steps; therefore, the later deposited metallization will be deposited through any holes or openings in the insulation layer formed in contact with the first deposited metallization.
Defects, such as open-circuits and short-circuits, can also occur in the FET associated with a pixel. For example, a layer of SiN insulates the gate of the FET from a layer of amorphous silicon through which a conductive channel, between the source and drain regions of the FET, is enhanced when a voltage of sufficient magnitude and proper polarity is applied to the FET gate with respect to the FET source. If an opening exists in the SiN insulation layer of the FET, a conductive path may be established between the gate or scan line and the corresponding data line through the FET, which path will adversely affect operation of the pixel associated with that FET.
The problem of short-circuits within the FET may be addressed by providing a redundant or auxiliary FET for each pixel. This remedy has certain disadvantages, however: Most of the pixels may not need a second FET; and, since the second FET is at all times connected between the pixel electrode and the data and scan lines, it causes additional capacitance to be present which may reduce the speed of operation of the device because of the increased RC time constant of the data lines. This problem will become even more critical as display areas become larger; longer address lines cause the line resistance to increase and the pixel capacitor will take longer to charge. Additionally, if both FETs are connected at all times and if there is a defect in one of the two FETs, it may not be possible to identify which FET has the defect because the defect may not be visible through a microscope. Therefore, there is a risk that the good FET will be severed from the address lines, i.e., the metal lines connecting the FET to the scan and data lines will be severed by the known technique of laser evaporation, when attempting to electrically isolate the defective FET.
It is accordingly a primary object of the present invention to provide a novel LCD structure which is not subject to the foregoing disadvantages.
It is another object of the present invention to provide auxiliary FETs which are electrically isolated from the LCD so as to not affect normal operation of the LCD un
less required.
It is yet a further object of the present invention to provide redundant scan and data line crossovers which are electrically open unless otherwise required.
It is yet another object of the present invention to provide laser-fusible links, for connecting the auxiliary FETs and for closing the redundant scan and data line crossovers, which can be efficiently formed during the LCD device fabrication without excessive process steps and which can be quickly and easily activated.
These and other objects of the invention, together with the features and advantages thereof, will become apparent from the following detailed specification when read with the accompanying drawings in which like reference numerals refer to like elements.